This repository contains the implementation of LDPC (Low-Density Parity-Check) Encoding and Decoding algorithms using Verilog. The project was undertaken as part of an ISRO internship and focuses on hardware-level deployment and simulation of LDPC processes.

This is an implementation of a min-sum LDPC decoder in Verilog. The current implementation is a length-10 code with 5 low-density parity check equations. The design rate is hence 0.5 info bits per bits transmitted. The min-sum algorithm iteratively solves the linear parallel parity-check equations. 5-10 iterations should be enough for convergence.

Low Density Parity Check Decoder. This is the LDPC decoder I developed for my ECEN 654 final project. It currently impliments a rate .5 code but is nearly fully parameterised so it could generate decoders for arbitrary H matrices with only minor changes.

Jan 1, 2015 · We present a routing approach for a parallel LDPC decoder implementation by 1) analyzing the physical routability limitations and 2) designing the code parameters to limit the interconnect...

Using the proposed methods, the implementation of encoders can become practical while keeping the hardware complexity of the partly parallel decoder structures. An encoder and a decoder are designed using Verilog-HDL and are synthesized using a 0.35 µm CMOS standard cell library.

The LDPC IP is a specialized encoder and decoder for Low-density parity-check codes, specifically designed for the 802.3an standard. Within the IEEE 802.3an 10GBASE-T standard, the (2048,1723) RS-LDPC code has been integrated as the designated forward error correction technique. Making customer’s design complete faster, lower cost and more robust.

LDPC codes were developed in 1960 by Robert Gallager at MIT in his PhD thesis. LDPC codes were forgotten until his work was rediscovered in 1996 and gradually it became the coding scheme of choice in the late 1990s, used for applications such as the Deep Space Network and satellite communications. 1.1 Error Detection and Correction

A min-sum LDPC decoder written in SystemVerilog (IEEE 1800-2012) - adimitris/verilog-LDPC-decoder

Hardware implementation aspects of highly flexible low-density parity-check (LDPC) encoder and decoder are presented. The paper covers algorithmic and architectural approaches in achieving flexible and yet very efficient LDPC codec solutions in terms of hardware usage efficiency (HUE).

Aug 6, 2014 · Each K bit/symbol user block is mapped (encoded) into an N bit/symbol codeword, where N > K . . . = ... ... ... ... 0 0 ... ⎢ ⎢ ... ... ... Normally, for each erroneous symbol, decoder has to determine that the symbol is in error and find the correct symbol value.