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IEEE15d
Impact evaluation of logic blocks configuration on FPGA's soft error rate estimation
Abstract: The Soft Error Rate (SER) of an electronic system depends on its sensitivity to the transient faults on its internal elements. Therefore, the SER is ...
IEEE27d
An ultra-dense irradiation test structure with a NAND/NOR readout chain for characterizing soft error rates of 14nm combinational logic circuits
Abstract: This paper describes a 14nm test chip employing a novel NAND/NOR readout chain for characterizing soft error rate (SER) in combinational logic gates. The ...