Verilog could on occasion call the Tclevent loop, or it could set itself up and rely on the Tcl event loop tocall it. Having multiple event loops can be awkward, but might bedesirable for raw Verilog ...

Some efforts have been done previous to this work in porting HDLs to C/C++ platform [1-3]. VTOC from Tension [3] is a commercial tool that converts Verilog to C++/SystemC. VTOC converts Verilog RTL to ...

What I wound up with is a reasonably portable Verilog logic analyzer that can produce traces like this one: Keep in mind, this isn’t a simulation. This is real data pulled off the actual FPGA.