The following four steps are proposed to raise the abstraction level of current Verilog HDL designs and provide a phase wise approach for Verilog designers to gradually migrate to SystemVerilog: 1.

IEEE Std. 1364-2001 standard for the Verilog Hardware Description Language, IEEE, Pascataway, NJ, 2001. IEEE P1800 Std. for SystemVerilog Hardware Description Language. SystemVerilog for Design: A ...