These quanta (call them packets or transactions) could be single bit operations (like a single logic level plus time interval on a USART TX bit) or complex operations involving multiple clock cycles ...

Faster runtime performance, real-time access to built-in Verilog simulation coverage metrics, and a unified graphical environment for waveform analysis are all promised by version 5.0 of the VERA ...

TestBencher Pro v8.0 adds support for mixed C++ and hardware description language (HDL) test benches using the open standard TestBuilder library. This library offers useful verificatio ...