In this paper an optimized power gating design on a 55-nm Static Random Access Memory (SRAM) compiler is presented. Two low leakage modes: retention and sleep mode are discussed. The arrangement of ...
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It comprises of existing VLSI PLus IP cores, optimized ... VeriSilicon SMIC 0.13um Synchronous programmable diffusion ROM optimized for Semiconductor Manufacturing International Corporation (SMIC) ...
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The proposed 8-kb static random address memory (SRAM) CIM macro is implemented using 28-nm CMOS technology. It can achieve an energy efficiency of 224.4 TOPS/W and an area efficiency of 21.894 TOPS/mm ...
Persistent Link: https://ieeexplore.ieee.org/servlet/opac?punumber=92 ...
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