today announced the release of the DVT Debugger Add-On Module for the e language, SystemVerilog, Verilog, and VHDL, which simplifies and speed up code debugging. Design and Verification Tools (DVT) is ...

Integrated SystemC (TM) debugging Riviera 2004.12 has extended the support for SystemC by allowing designers to instantiate VHDL and Verilog modules in SystemC code, providing complete coverage of all ...