The AVR128DA28 that’s used here tops out at 24 MHz (double that if you use the PLL) but [David] got reliable results from his clock divider feeding a signal as high as 90 MHz to the input pin.

As a demonstration of the complex circuits possible with our NOR gates, six two-input, one-output digital logic circuits were built by integrating up to five NOR gate cassettes into various ...

FDSOI FET allows the threshold voltage ( V t) to be adjustable (i.e., low-Vt and high-Vt states) by using the back gate bias. Our design utilizes the front and back gates of an FDSOI FET as the input ...

The printed logic gates were reliable even after thousands of switching cycles. Velásquez-García explained that manufacturers could use this method in cheap devices that don't need the "best ...