The device is available as Verilog source code, and as a netlist for Xilinx FPGAs. Several additional Viterbi decoder devices addressing different markets and even higher throughput are expected to be ...

The LDPC IP Core supports code rates 1/2, 2/3 and 4/5 ... The CCSDS AR4JA LDPC Encoder and Decoder IP Core is available immediately in synthesizable Verilog or optimized netlist format, along with ...