The Clocked SR (Set-Reset) Flip-Flop or Clocked RS Flip-Flop is an upgraded version of the SR or RS latch, which adds clock ...

In the present work, a low-power, high-performance asynchronous counter is designed, implemented and simulated using reversible logic. This reversible logic gates such as Feynman, Fredkin and Sayem ...

We propose a low area overhead and power-efficient asynchronous-logic quasi-delay-insensitive (QDI) sense-amplifier half-buffer (SAHB) approach with quad-rail (i.e., 1-of-4) data encoding. The ...