This brief presents a 14-bit 4 GS/s time-interleaving ADC design using two interleaved sub-ADCs. The sub-ADC achieves 2 GS/s conversion rate in 28 nm CMOS technology and uses pipelined structure to ...

The CML based (triple tail and folded) D flipflop and conventional NAND based D-flipflop are implemented at 45 nm technology with a comparative analysis with respect to power and propagation delay. It ...