News

EDN15y
Using Tcl to create a virtual component in Verilog
Any processing done in the client consumes no time from the perspective of Verilog. We adopt this simplified concept of time to synchronize two asynchronous processes. The transaction serves as a sort ...
Hackaday6y
Learn Verilog In Your Browser
The HDLBits site has a great set of Verilog “exams” that would be a big help to anyone trying to learn or brush up on their Verilog skills. The site offers a range of topics that go from the ...
Hackaday9y
Learning Verilog For FPGAs: Hardware At Last!
In the previous pair of installments in this series, you built a simple Verilog demonstration consisting of an adder and a few flip flop-based circuits. The simulations work, so now it is time to ...
Design-Reuse19y
Reusing Verilog IP Cores in SystemC Environment by V2SC
VTOC from Tension [3] is a commercial tool that converts Verilog to C++/SystemC. VTOC converts Verilog RTL to C++/SystemC by interleaving the processes in order to achieve fast simulation speed. V2SC ...
Electronics Weekly17y
Using Verilog-A simulation in analogue design
A key part of any analogue design flow is having models of the components for simulation. Traditional Spice models of basic components such as transistors and capacitors written in C or C++ are ...