News

Hackaday6y
Visualizing Verilog Simulation - Hackaday
You don’t usually think of simulating Verilog code — usually for an FPGA — as a visual process. You write a test script colloquially known as a test bench and run your simulation.… ...
Hackaday9y
Learning Verilog For FPGAs: The Tools And Building An Adder
Choose a Verilog Simulator EDA Playground Simulates Verilog in the Browser. For part I, you need a Verilog simulator. I’m going to use EDAPlayground because it is free and it will run in your ...
EDN21y
Lighthouse introduces synthesis tools for Verilog test - EDN
SANTA CRUZ, Calif. — Promising to reduce testbench development time by up to 80 percent, startup Lighthouse Design Automation Inc. this coming week will introduce tools that synthesize Verilog ...
EDN19y
SIMULATION: Verilog simulator becomes open-source item
Santa Cruz, Calif. — In the 1990s, Elliot Mednick pioneered low-cost Verilog simulation. Now he's made his VeriWell simulator a free, open-source offering available through the Sourceforge Web site.
Business Wire16y
Aldec Brings Assertions to FPGA Designers with the Release of Active-HDL 8.1 - Business Wire
Verilog Simulation Speed-up. Verilog simulation speed at the gate level has been increased up to 2.3X over the previous releases by using the advanced optimization settings available ...
Electronic Design3y
HDL Environment Adds Direct Compile Verilog Simulator
The Active-HDL design environment now includes Active-HDL/VLOG, a stand-alone, IEEE 1364-95 Verilog-compliant simulator. The new Verilog simulation kernel includes Verilog design entry, test-bench ...
Electronic Design23y
Verilog Simulator Adds Full-Featured Coverage Analysis And A C/C++ Interface - Electronic Design
The latest VCS Verilog simulator from Synopsys contains built-in comprehensive coverage analysis. With it, design teams using VCS 6.0.1 can determine their verification quality before tapeout ...
Design-Reuse23y
Synopsys VCS Verilog Simulator Incorporates Breakthrough Verification Capabilities - Design And Reuse
Synopsys VCS Verilog Simulator Incorporates Breakthrough Verification Capabilities. MOUNTAIN VIEW, Calif.--(BUSINESS WIRE)--Sept. 26, 2001-- Synopsys, Inc. (Nasdaq:SNPS), the technology leader for ...
Business Insider5y
SmartDV Adds Support for Verilator Open Source HDL Verilog Simulator
SAN JOSE, Calif., Oct. 01, 2019 (GLOBE NEWSWIRE) -- SmartDV™ Technologies today announced support for Verilator, the free, open-source hardware description language (HDL) simulator, becoming the ...
Design-Reuse1y
Fintronic Announces Verilog Separate Compilation For FinSim Simulator
Dr. Graham Hellestrand, CEO of VaST Systems Technology Corp, leading provider of System Level platforms and tools for pre- and post-silicon embedded systems engineering stated: "I am very pleased that ...
Semiconductor Engineering3y
A brief history of logic simulation - Semiconductor Engineering
Phil Moorby, one of the creators of Hilo 2, left GenRad and started to work for Gateway Design Automation. In 1984 he created the Verilog hardware description language (HDL). This was the first ...