There is an exception to this. During simulation, Verilog does act like a programming language, but it has very specific rules for keeping the timing the same as it will be on the FPGA.

Special code must be written t o interface with the specific Verilog Programming Language Interface (PLI) to drive and sample simulation signals at the appropriate simulation time. Moreover, ...

It should be noted, however, that Z01X! is not fully IEEE compliant because it doesn't support the Verilog programming language interface (PLI). “We are not great believers in the PLI,” said Williams.

Nazeih Botros’s HDL Programming Fundamentals provides a basic course in both VHDL and Verilog. There’s a slew of books out there that take up either one language or the other; this one is a ...