So the code instructs the FPGA (or, more accurately, the Verilog compiler) to examine the number and set dispoutput based on the input. The <= character, by the way, are a non-blocking assignment.

This paper focuses on the implementation and simulation of 4-bit, 8-bit and 16-bit carry look-ahead adder based on Verilog code and compared for their performance in Xilinx. ...

Design and Testing of Prefix Adder for High Speed Application by Using Verilog HDL. Parallel prefix adder is the most flexible and widely used for binary addition.