Thus, a supply of 25-35V is a good choice to generate the square wave signal applied to the two ends of the test wire. Figure 2 Schematic diagram of wire break detector using CMOS memory cell (shown ...

A NAND gate can of course be realized by adding M2 and R3 to form an output inverter. Figure 3 Two-input NAND gate (a), and MOSFET realization (b) For a more analog MOSFET application, consider this ...

The first circuit to be created is 'Invert', that is, a circuit that outputs '0' for the input of '1' and '1' for the input of '0'. The NAND gate is a circuit that outputs '0' when both inputs are ...

Therefore, by forcing input B to a logic low, Q2 is always closed and Q6 is always opened, and you can use A as input 1 and C as input 2, with the gate working as a two-input CMOS NAND gate.