SAN MATEO, Calif. — Cadence Design Systems Inc. has introduced the Transistor Logic Abstracter (TLA), which generates logic-level Verilog functional models from Spice or Spectre transistor-level ...

TestBencher Pro provides a graphical environment for rapidly generating system-level test benches composed of cycle-based or time-based bus functional models ... VHDL and Verilog test benches ...

Over the past year, Model Technology has made significant strides in the Verilog gate-level simulation market. We're emerging as an industry leader, and Hitachi, and other ASIC partners, realize that ...

SAN MATEO, Calif. — Cadence Design Systems Inc. has introduced the Transistor Logic Abstracter (TLA), which generates logic-level Verilog functional models from Spice or Spectre transistor-level ...