Lowest power mode (Standby) PD1/PD2 domain is power gated, so all flops in PD1/PD2 domain must get a reset on exit from standby mode. If exit from standby is via a non-reset source then the flops in ...

This used a STi7108 [6] as the SoC and an ST8 based CPU as the external controller. This is represented in Fig 13. The CPS architecture was presented using deployment models to provide the state of ...