As a result, both power and area of the De-serializer can be reduced by using a DLL in the clock recovery circuit. Since the required high-speed serial clock is available from the shared PLL, both the ...

The System Packet Interface--Scaleable (SPI-S) is the next-generation interface developed by the OIF to take advantage of serialization of physical interconnects. Figure 1. System Block Diagram ...

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To further reduce the number of interconnecting wires from seven to three, plus a ground return, you can adapt a configurable serializer/deserializer such as National Semiconductor's LM2501. The ...