The nodes communicate with each other via mesh networking; the implementation is capable of scaling up to a 64x64 array (4,096 processors). Adapteva claims that Epiphany is capable of delivering ...

The International Solid-State Circuit Conference (ISSCC) always features outstanding papers on a wide range of topics. A classic example from ISSCC 2006 is a paper presented by a research group led by ...

Intel shows 80-core parallel processor array. ... The 65nm 100 million transistor 4GHz device includes an 8×10 array of ‘processing engines’ (PEs), each consisting of two 32-bit floating-point ...

Adapteva's 1-GHz E16G301 Epiphany delivers 32 GFLOPS using a 16-core array of 32-bit, single precision floating-point processors linked by a communication mesh that can expand ...

Over at Cluster Monkey, Douglas Eadline writes that the “free lunch” performance boost of Moore’s Law may indeed be back with the 1024-core Epiphany-V chip that will hit the market in the next few ...

VeriSilicon announces Vivante CC8000, a dedicated IP series based on highly parallel, scalable MESH processor architecture with the highest GFLOPS. VeriSilicon announces Vivante CC8000, ...

Along with the new mesh, which enhances the connectivity and topology of the on-chip interconnect, Intel is implementing a modular architecture with its Xeon Scalable processors for resources that ...

AMD has unveiled its Epyc 4005 processor series, designed to support a broad array of enterprise solutions. The slimmed down product portfolio is comprised of six different offerings, with the new ...