Of course, what I've just described is only one way to use the DQM, counters, extended tag RAM, and other QoS hardware in order to enforce cache usage constraints on a per-thread basis.

The guest OS maps virtual memory to real memory via its page tables, and the VMM page tables map the guests’ real memory to physical memory. The virtual memory architecture is specified either via ...

If the L2 TLB misses, a hardware algorithm is used to walk the page table and update the TLB entry. In the worst case, the page is not in memory, and the operating system gets the page from disk.