Of course, what I've just described is only one way to use the DQM, counters, extended tag RAM, and other QoS hardware in order to enforce cache usage constraints on a per-thread basis.

The guest OS maps virtual memory to real memory via its page tables, and the VMM page tables map the guests’ real memory to physical memory. The virtual memory architecture is specified either via ...

The memory hierarchy of the Cortex-A8 was simulated with 32 KB primary caches and a 1 MB eight-way set associative L2 cache using the integer Minnespec benchmarks (see KleinOsowski and Lilja [2002]).