Adam Kablanian is CEO of Virage Logic in Fremont, Calif. An emerging semiconductor intellectual property (SIP) market that is picking up momentum due to the rise of the Internet and communications is ...

As an example, Saggurti says, “In CMOS we were taught not to have more than four transistors stacked together, so a four-input NAND gate was the maximum. Now, with finFET, a stack is actually a good ...

Memory Hierarchy Design – Part 3. Memory technology and optimizations, which examined innovations in main memory that offer improved system performance; This installment, which examines architecture ...

Memories are increasingly grouped into multi-die configurations such as multi-chip modules (MCMs) and 2.5D/3D structures, posing significant challenges to design, analysis, and packaging. For example, ...

Memory timing behavior can have a significant impact on how a system's memory system is designed. For example, if you think of memory requests as cars, you don't want to have a traffic jam -- so ...

A new design for computer memory that could both greatly improve performance and reduce the energy demands of internet and communications technologies, which are predicted to consume nearly a third of ...

In short, allocating memory on these machines is always tricky—with a new entrant like stacked memory into the design process, it is useful to gauge where 3D devices might fit. While stacked memory is ...

TORONTO — If there is one enduring trend for memory design in 2014 that will carry through to next year, it’s the continued demand for higher performance. “The trend toward high performance is never ...

Micron’s Atlanta Design Center, which will open for business in January 2022, will create up to 500 jobs across various STEM disciplines, including computer hardware and electrical and ...