The new Verilog simulation kernel includes Verilog design entry, test-bench generation ... Other features include state machine and block-diagram editors, automatic test-bench generation ...

The kernel supported within the Active-HDL design environment includes Verilog ... The Active-HDL/VLOG includes state machine and block diagram editors, graphical data flow, advanced Verilog debugging ...

With Active-HDL/DL designers can freely mix, simulate and debug VHDL, Verilog and EDIF at all levels of a design's hierarchy ... HDL Editor, Block Diagram Editor, Automatic Testbench generator ...