Verilog provides an initial block that is usually not valid for synthesis, but will be the main part of most test benches. Here’s the first part of it: The two $ statements tell the testbench to ...

but this combination may be used in an initial block for implementing a test-bench that is supported as described in 5.4. 5.4. Test-Benches Generally a Verilog test-bench is an initial block where ...