Managing the power consumption of ICs is an increasingly difficult challenge, because each new generation of portable device includes expanded features and demands longer battery lives.

As system-on-chip (SoC) designs grow larger, designers must grapple with serious global timing problems, the effect of wire loading and timing delays and the performance hit associated with supporting ...

The first day of the conference was billed as an “Industry Day” with topics chosen to suit companies that are likely doing synchronous digital design with an interest toward learning more about ...

This architecture has become so ubiquitous that it is considered by many to be the only way to design digital circuits. There is, however, an altogether different ... technologies. As silicon ...

Like adiabatic circuits, asynchronous circuits are a promising technology for low-power, highly modular digital circuits. In contrast to synchronous circuits which operate according to clock timing ...

A software tool for automatically converting synchronous circuit designs into asynchronous equivalents is being developed by researchers at the University of Edinburgh. Asynchronous ICs – which do not ...

Null Convention Logic (NCL): An asynchronous design paradigm that uses delay-insensitive methods to enhance power efficiency and robustness in digital circuits. GALS (Globally Asynchronous Locally ...

Micropipelines. Ivan E. Sutherland: The Turing Award Lecture. Communications of the ACM, Vol. 32, No. 6, pages 720¿738; June 1989. Asynchronous Circuits and Systems. Special issue of Proceedings ...

Asynchronous design gets a second look By Bernard Cole, EE Times June 9, ... flash, digital logic, programmable logic and analog circuitry — the job of maintaining the global clocking across the area ...